Work Description - Vlsi Mixed Signal Tester

The Semi-Conductor Laboratory (SCL), a Central Government Ministry/Department, invites Global Tenders (Tender ID: 2024_SCL_833876_1, Reference Number: SCL/PS/45063/VTAD/2024) for the supply of a VLSI Mixed Signal Tester. Interested bidders can download tender documents from November 6th, 2024, 6:35 PM to December 5th, 2024, 4:00 PM. Bid submission opens on November 6th, 2024, 6:35 PM and closes on December 5th, 2024, 4:00 PM, with bid opening scheduled for December 6th, 2024, 4:00 PM at the Semi-Conductor Laboratory. A fixed EMD of ₹5,00,000 is required, payable to the Semi-Conductor Laboratory (SCL), with BG/ST or EMD exemption allowed. The tender fee is ₹0.00. The contract is for supply and has a 210-day work period and 120-day bid validity. Multi-currency is allowed for BOQ but not for fees. Contact Anil Budhwar, SPSO, at Semi-Conductor Laboratory for further inquiries. The tender comprises two covers: one for commercial terms and conditions and another for the Bill of Quantities (BOQ). Please refer to the tender documents for details on NDA/Pre-Qualification requirements.